Hardware implementation of a low cost math module using multifunctional registers with decoded mode inputs

Abstract

In the present paper, we propose a low cost algorithm of a math module and the implementation using multifunctional registers with decoded mode inputs. The proposed math module algorithm will be implemented using the transition matrix method. According with taxonomy of the algorithms, we use the functional iteration one. It is found in specific literature that it can provide the lowest latency and greatest reliability. Compared with CORDIC math module which is based on the hardware iteration algorithm with design implemented in FPGA (which is more expensive and slow than a dedicate hardware), our proposed math module algorithm use less hardware, means the chip area is minimized, working at a high speed rate.
There, will be proved that implementation of the digital automaton can be reduced to a combinational one, this will lead to the economical implementation.